1. Field of the Invention
The present invention relates to memory control devices that control SDRAM and other synchronous memory devices as well as image forming devices equipped with such memory control devices.
2. Description of the Related Art
Recent electric devices operate with the aid of a CPU of a personal computer (hereinafter referred to as “PC”) or a CPU incorporated in a printer or the like. The CPU processes and controls a variety of data. Operating frequencies of the system clock (reference clock) in the CPUs are constantly increasing to increase the processing speed. However, higher clock frequencies result in generation of greater electromagnetic interference in the electronic device. Electromagnetic interference has a negative effect on other operations in the device and on other electronic devices.
Recently, modulated clocks are used as operating clocks to suppress electromagnetic interference. Modulated clocks are generated by Spread Spectrum Clock (SSC) technology. The SSC technology modulates the reference clock to spread and fall within a narrow band such that the modulated clock periodically changes its clock frequency by a few percent. The change in clock frequency suppresses the peak of electromagnetic interference, as disclosed in Japanese patent application publication No. 2000-280575.
CPUs designed to operate in accordance with input clocks can use the modulated clocks as they are. Recently, however, input clocks are used upon multiplying the input clocks with the use of a PLL (phase locked loop) circuit built-in CPU rather than using the input clocks as they are. The use of the modulated clocks generated by the SSC technology in the PLL circuit built-in CPU may cause the PLL to unlock the PLL. As a result, clocks with a desired frequency cannot be obtained.
For this reason, a CPU with the built-in PLL circuit and circuits that exchange signals directly with the CPU are supplied with the reference clocks while other circuits are supplied with the modulated clocks. This configuration does not lower the peak of electromagnetic interference generated from reference clock lines, but lower the peak of electromagnetic noise generated from modulated clock lines. Thus overall electromagnetic interference is suppressed.
Although the use of both a reference clock and a modulated clock reduces electromagnetic interference, this approach has some disadvantages. For example, a synchronous memory that operates in synchronization with an external clock may not operate normally. There are several types of synchronous memories, such as synchronous. ROM (SROM), synchronous static RAM (SSRAM), synchronous dynamic RAM (SDRAM), etc. Due to large storage space and low cost, the SDRAMs are often used as a main memory in PCs, printers, and other electronic devices.
The SDRAMs are normally controlled by a dedicated memory control circuit. This memory control circuit outputs commands to the SDRAM based on commands that the circuit receives from the CPU. The memory control circuit is normally formed in an ASIC (Application Specific Integrated Circuit) or other integrated circuit.
Since the memory control circuit exchanges various signals and data with the CPU and is often mounted relatively close to an oscillator (i.e., the oscillator and the ASIC are located in positions close to each other on the circuit board) that generates reference clocks, the memory control circuit operates in synchronization with the reference clocks.
The SDRAM, on the other hand, is often configured as a DIMM (Dual Inline Memory Module) or similar module and is therefore often located on a portion of the circuit board that is some distance away from the CPU or ASIC.
As shown in FIG. 3, the length of reference clock line Lc3 from an oscillator 35 to an SDRAM 33 via an ASIC 34 is longer than the length of reference clock line Lc1 from the oscillator 35 to a CPU 31 and the length of reference clock line Lc2 from the oscillator 35 to the ASIC 34. With this configuration, a spread spectrum clock generator (SSCG) is provided in the ASIC 34 to thereby generate modulated clocks while modulating reference clocks. The modulated clocks are supplied from the ASIC 34 to the SDRAMs 33 to operate the latter in synchronization with the modulated clocks.
The memory control circuit outputs various control signals and writes and reads data to and from the SDRAM in synchronization with the reference clock while the SDRAM, that is controlled by the memory control circuit, operates in synchronization with the modulated clocks. As a result, there are risks that the control signals from the memory control circuit are not properly received, that data write/read operations do not end normally, or that the SDRAM may not operate normally.
More specifically, when the SDRAM operates in synchronization with reference clocks, as shown in FIG. 6(a), there is enough setup time and hold time before a reference clock signal rises. This enables the SDRAM to latch control signals and interpret the command. Note that FIGS. 6(a) through 6(c) show only a chip select signal cs#. However, when the SDRAM operates in synchronization with modulated clocks, the hold time is reduced as shown in FIG. 6(b) or the setup time is reduced as shown in FIG. 6(c). Although there seems to be enough setup time in FIG. 6(c), a setup time longer than the hold time must be provided. For this reason, it is not desirable that the setup time become shorter than the predetermined setup time shown in FIG. 6(a).
Thus the SDRAM operating in synchronization with the modulated clocks reduces the setup or hold times. As a result, latching control signals and data by the SDRAM is not assured.